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Defect localization at transistor gate using electron beam induced resistance change (EBIRCh)

Over the last decade, Electron Beam Induced Resistance Change (EBIRCh) has been an important addition to the family of Failure Analysis (FA) techniques. It is used to map resistance behavior of the sample, i.e. how the resistance of the sample changes over electron beam exposure. EBIRCh can be used to locate all types of defects sensitive to the electron beam. But it is at its best at localizing high resistive defects in oxides, which can be difficult to do with other techniques. In this note, we report about an experiment where EBIRCh was used to localize a defect within the gate oxide of a transistor.

To monitor the resistance of the sample, a small current (300pA) was applied between the gate and bulk probes. Such a small current minimizes risks of defects modifications, while still being detectable by the high-sensitivity current amplifier (Point Electronic).

The resistance behavior of the sample is then mapped into an image, displaying resistance changes as bright red spots over a dark background. The location of the defect in the gate oxide was identified as a 59nm spot. The high accuracy of the defect localization obtained in this case allows the failure analyst to be certain that the defect will be contained in a single TEM lamella prepared from the vicinity of the spot, avoiding the preparation and observation of several TEM lamellas not containing the defect.

Experiment realized in partnership with

Dialog Semiconductor PLC

Point Electronic GmbH

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Imina Technologies' application engineer shows a colleague how to land probes on nanoscale contacts for in-situ SEM transistor characterization.