Components of VLSI circuits often suffer from mechanical stress that appears during fabrication and packaging. For example, OFF-state leakage current of CMOS can significantly increase leading to higher power consumption and lower device reliability and lifetime.
To understand the effects of mechanical stress in MOSFET devices, Kookjin Lee and his colleagues from KU Leuven and imec measured the changes of gate-induced drain leakage in mechanically stressed samples. To do that, they combined 4 microprobers with a nanoindenter.
“When the miBots and nanoindenter are used together, electrical characterization can be done while localized mechanical stress up to GPa-level is applied to the device. This approach opens up a new chapter on the combined mechanical stress and electrical measurements.” – Says Kookjin Lee.
It is known that mechanical stress changes the band structure. In case of these MOSFET devices, it increases band-to-band tunneling of charge carriers in the overlap region between gate and drain. The researchers observed an exponential increase of gate-induced drain leakage (GIDL) produced by vertically applied mechanical stress. The effect was pronounced the most when the force was applied to the area of the device channel. This knowledge can be used to optimize the device architecture and insure longer and safer operation.