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Threefold speed-up in the characterization of 7 nm SRAM transistors using an XYZ sample substage

Nanoprobing of small technology-node devices can be very time-consuming. To navigate around the sample and to contact the device under test, one has to operate the SEM under low acceleration voltage and short working distance. These imaging conditions result in comparatively poor image contrast, slowing the operator down.

Sample Positioning XYZ Sub-Stage significantly speeds up the process. It helps to quickly move from one ROI to another without having to move the probers one by one. It also helps to approach or to retract the sample to/from the probers much faster.

We show that with the Sample Positioning XYZ Sub-Stage, the characterization of NMOS transistors of a 7 nm semiconductor technology nodes is three times faster than without the Sub-Stage.

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